SH7146 Datasheet, PDF (955/1022 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 24 Electrical Characteristics
24.3.2 Control Signal Timing
Table 24.6 Control Signal Timing
Conditions: V_CC = 4.0 V to 5.5 V, AV_CC = 4.0 V to 5.5 V, V_SS = PLLV_SS = AV_SS = 0 V,
T_a = –20°C to +85°C (consumer applications)*⁵,
T_a = –40°C to +85°C (industrial applications)
Item
Symbol Min.
Max.
Unit Reference Figure
RES pulse width
t_RESW
20*²
—
t *4
Bcyc
Figures 24.3, 24.4,
RES setup time*¹
t_RESS
65
—
ns
24.6, 24.7
RES hold time
t_RESH
15
—
ns
MRES pulse width
MRES setup time*¹
MRES hold time
t_MRESW
20*³
—
t_MRESS
25
—
t_MRESH
15
—
t *4
Bcyc
ns
ns
MD1, MD0, FWE setup time
t_MDS
20
—
t *4
Bcyc
Figure 24.6
BREQ setup time
t_BREQS
1/2t_Bcyc + 15 —
ns
Figure 24.9
BREQ hold time
t_BREQH
1/2t_Bcyc + 10 —
ns
NMI setup time*¹
t_NMIS
60
—
ns
Figure 24.7
NMI hold time
t_NMIH
10
—
ns
IRQ3 to IRQ0 setup time*¹
t_IRQS
35
—
ns
IRQ3 to IRQ0 hold time
IRQOUT output delay time
BACK delay time
t_IRQH
35
t_IRQOD
—
t_BACKD
—
—
ns
100
ns
1/2t_Bcyc + 20 ns
Figure 24.8
Figures 24.9, 24.10
Bus tri-state delay time
t_BOFF
0
100
ns
Bus buffer on time
t_BON
0
100
ns
Notes: 1. The RES, MRES, NMI, BREQ, and IRQ3 to IRQ0 signals are asynchronous signals.
When the setup time is satisfied, change of signal level is detected at the rising edge of
the clock. If not, the detection is delayed until the rising edge of the clock.
2. In standby mode, t_RESW = t_OSC2 (10 ms).
3. In standby mode, t_MRESW = t_OSC2 (10 ms).
4. t indicates external bus clock cycle time (Bφ = CK).
Bcyc
5. –20°C to +75°C for SH71491.
Rev. 3.00 May 17, 2007 Page 911 of 974
REJ09B0229-0300