SH7146 Datasheet, PDF (39/1022 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Table 9.8
Table 9.9
Minimum Number of Idle Cycles between CPU Access Cycles
in Normal Space Interface .................................................................................... 224
Minimum Number of Idle Cycles between Access Cycles
during DTC Transfer for the Normal Space Interface .......................................... 225
Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 10.1 MTU2 Functions................................................................................................... 234
Table 10.2 Pin Configuration.................................................................................................. 239
Table 10.3 Register Configuration.......................................................................................... 240
Table 10.4 CCLR0 to CCLR2 (Channels 0, 3, and 4) ............................................................ 245
Table 10.5 CCLR0 to CCLR2 (Channels 1 and 2) ................................................................. 245
Table 10.6 TPSC0 to TPSC2 (Channel 0) .............................................................................. 246
Table 10.7 TPSC0 to TPSC2 (Channel 1) .............................................................................. 246
Table 10.8 TPSC0 to TPSC2 (Channel 2) .............................................................................. 247
Table 10.9 TPSC0 to TPSC2 (Channels 3 and 4) ................................................................... 247
Table 10.10 TPSC1 and TPSC0 (Channel 5)........................................................................ 248
Table 10.11 Setting of Operation Mode by Bits MD0 to MD3 ............................................ 250
Table 10.12 TIORH_0 (Channel 0) ...................................................................................... 253
Table 10.13 TIORL_0 (Channel 0)....................................................................................... 254
Table 10.14 TIOR_1 (Channel 1) ......................................................................................... 255
Table 10.15 TIOR_2 (Channel 2) ......................................................................................... 256
Table 10.16 TIORH_3 (Channel 3) ...................................................................................... 257
Table 10.17 TIORL_3 (Channel 3)....................................................................................... 258
Table 10.18 TIORH_4 (Channel 4) ...................................................................................... 259
Table 10.19 TIORL_4 (Channel 4)....................................................................................... 260
Table 10.20 TIORH_0 (Channel 0) ...................................................................................... 261
Table 10.21 TIORL_0 (Channel 0)....................................................................................... 262
Table 10.22 TIOR_1 (Channel 1) ......................................................................................... 263
Table 10.23 TIOR_2 (Channel 2) ......................................................................................... 264
Table 10.24 TIORH_3 (Channel 3) ...................................................................................... 265
Table 10.25 TIORL_3 (Channel 3)....................................................................................... 266
Table 10.26 TIORH_4 (Channel 4) ...................................................................................... 267
Table 10.27 TIORL_4 (Channel 4)....................................................................................... 268
Table 10.28 TIORU_5, TIORV_5, and TIORW_5 (Channel 5)........................................... 269
Table 10.29 Setting of Transfer Timing by BF1 and BF0 Bits............................................. 291
Table 10.30 Output Level Select Function ........................................................................... 304
Table 10.31 Output Level Select Function ........................................................................... 305
Table 10.32 Setting of Bits BF1 and BF0............................................................................. 307
Table 10.33 TIOC4D Output Level Select Function ............................................................ 307
Table 10.34 TIOC4B Output Level Select Function............................................................. 308
Table 10.35 TIOC4C Output Level Select Function............................................................. 308
Rev. 3.00 May 17, 2007 Page xxxix of xliv