SH7146 Datasheet, PDF (487/1022 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
10.7.10 Contention between TGR Write and Input Capture
If an input capture signal is generated in the T2 state of a TGR write cycle, the input capture
operation takes precedence and the write to TGR is not performed for channels 0 to 4. For channel
5, write to TGR is performed and the input capture signal is generated.
Figures 10.127 and 10.128 show the timing in this case.
MPφ
Address
Write signal
Input capture
signal
TCNT
TGR write cycle
T1 T2
TGR address
M
TGR
M
Figure 10.127 Contention between TGR Write and Input Capture (Channels 0 to 4)
MPφ
Address
Write signal
Input capture
signal
TCNT
TGR
TGR write cycle
T1 T2
TGR address
M
TGR write data
N
Figure 10.128 Contention between TGR Write and Input Capture (Channel 5)
Rev. 3.00 May 17, 2007 Page 443 of 974
REJ09B0229-0300