SH7146 Datasheet, PDF (678/1022 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 16 Compare Match Timer (CMT)
16.3 Operation
16.3.1 Interval Count Operation
When an internal clock is selected with bits CKS1 and CKS0 in CMCSR and the STR bit in
CMSTR is set to 1, CMCNT starts incrementing using the selected clock. When the values in
CMCNT and CMCOR match, CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set
to 1. When the CMIE bit in CMCSR is set to 1, a compare match interrupt (CMI) is requested.
CMCNT then starts counting up again from H'0000.
Figure 16.2 shows the operation of the compare match counter.
CMCNT value
CMCOR
Counter cleared by compare
match with CMCOR
H'0000
Time
Figure 16.2 Counter Operation
16.3.2 CMCNT Count Timing
One of four internal clocks (Pφ/8, Pφ/32, Pφ/128, and Pφ/512) obtained by dividing the Pφ clock
can be selected with bits CKS1 and CKS0 in CMCSR. Figure 16.3 shows the timing.
Peripheral operating
clock (Pφ)
Count clock
CMCNT
Nth
clock
(N + 1)th
clock
N
Figure 16.3 Count Timing
N+1
Rev. 3.00 May 17, 2007 Page 634 of 974
REJ09B0229-0300