SH7146 Datasheet, PDF (1006/1022 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Item
Page Revision (See Manual for Details)
17.1.6 Port D Control Registers L1 680,
to L4 (PDCRL1 to PDCRL4)
681
(SH7149 Only)
• Port D Control Register L4
(PDCRL4)
Deleted
Bit Bit Name Description
5 PD13MD1 PD13 Mode
4 PD13MD0 Select the function of the PD13/D13/AUDMD
pin. Fixed to AUDMD output when using the
AUD function of the E10A.
1 PD12MD1 PD12 Mode
0 PD12MD0 Select the function of the PD12/D12/AUDRST
pin. Fixed to AUDRST output when using the
AUD function of the E10A.
17.1.7 Port E I/O Registers L, H 686
(PEIORL, PEIORH)
17.1.8 Port E Control Registers L1 695
to L4, H1, H2 (PECRL1 to
to
PECRL4, PECRH1, PECRH2) 703
SH7149:
Table 17.13 Transmit Forms of 705
Input Functions Allocated to
Multiple Pins
Deleted
…. PEIORL is enabled when the port E pins are
functioning as general-purpose inputs/outputs (PE15 to
PE0), and the SCK pin pf SCI and the TIOC pin is
functioning as inputs/outputs of MTU2. In other states,
PEIORL is disabled.
Note added
Note: * This function is enabled only in the on-chip
ROM enabled/disabled external-extension
mode. Do not set 1 in single-chip mode.
Amended
OR Type
SCK0 to SCK2,
RXD0 to RXD2,
POE0, POE1,
POE4 to POE5, POE8
AND Type
IRQ0 to IRQ3, WAIT,
POE0, POE1,
POE4 to POE5, POE8
Rev. 3.00 May 17, 2007 Page 962 of 974
REJ09B0229-0300