SH7146 Datasheet, PDF (272/1022 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
9.5.6 Bus Arbitration
This LSI owns the bus mastership in normal state and releases the bus only when receiving a bus
request from an external device. This LSI has two bus masters: CPU and DTC. The bus
mastership is given to these bus masters in accordance with the following priority.
Request for bus mastership by external device (BREQ) > CPU > DTC > CPU
However, when DTC is requesting the bus mastership, the CPU does not obtain the bus mastership
continuously.
When the CSSTP2 bit is 1 in the bus function extending register (BSCHER), the external space
access request from the CPU has lower priority than the DTC transfer request with DTLOCK = 0
in the bus function extending register (BSCHER).
In addition, because the write buffer operates as described in section 9.5.7 (2), Access in View of
LSI Internal Bus Master, arbitration between the CPU and DTC is different depending on whether
the external space access by the CPU is a write or read access. Figure 9.10 shows the bus
arbitration when a DTC activation request is generated while an external space is accessed by the
CPU.
Rev. 3.00 May 17, 2007 Page 228 of 974
REJ09B0229-0300