SH7146 Datasheet, PDF (260/1022 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
9.5 Operation
9.5.1 Endian/Access Size and Data Alignment
This LSI supports big endian, in which the 0 address is the most significant byte (MSB) in the byte
data.
Two data bus widths (8 bits and 16 bits) are available. Data alignment is performed in accordance
with the data bus width of the respective device. This also means that when longword data is read
from a byte-width device, the read operation must be done four times. In this LSI, data alignment
and conversion of data length are performed automatically between the respective interfaces.
Tables 9.6 and 9.7 show the relationship between device data width and access unit.
Table 9.6 16-Bit External Device Access and Data Alignment
Data Bus
Operation
D15 to D8
D7 to D0
WRH
Byte access at 0 Data 7 to Data 0 
Assert
Byte access at 1 
Data 7 to Data 0 
Byte access at 2 Data 7 to Data 0 
Assert
Byte access at 3 
Data 7 to Data 0 
Word access at 0 Data 15 to Data 8 Data 7 to Data 0 Assert
Word access at 2 Data 15 to Data 8 Data 7 to Data 0 Assert
Longword 1st time Data 31 to Data 24
access at 0
at 0
2nd time Data 15 to Data 8
at 2
Data 23 to Data 16 Assert
Data 7 to Data 0 Assert
Strobe Signals
WRL

Assert

Assert
Assert
Assert
Assert
Assert
Rev. 3.00 May 17, 2007 Page 216 of 974
REJ09B0229-0300