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| SH7146 Datasheet, PDF (1005/1022 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family | |||
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Item
Table 17.10 SH7149 Pin
Functions in Each Operating
Mode (1)
Page Revision (See Manual for Details)
649 Deleted
Pin Name
On-Chip ROM Disabled
(MCU Mode 0)
On-Chip ROM Disabled
(MCU Mode 1)
Pin Initial
No. Function
PFC Selected
Function
Possibilities
Initial
Function
PFC Selected
Function
Possibilities
30 PD12/
PD12/D12
(AUDRST*2)
29 PD13/
(AUDMD*2)
PD13/D13
D12/
PD12/D12
(AUDRST*2)
D13/
PD13/D13
(AUDMD*2)
Table 17.11 SH7149 Pin
652
Functions in Each Operating
to
Mode (2)
655
17.1.2 Port A Control Registers L1 663
to L4 (PACRL1 to PACRL4)
to
SH7149:
670
17.1.4 Port B Control Registers 675
L1, L2, H1 (PBCRL1, PBCRL2, to
PBCRH1)
678
SH7149:
17.1.5 Port D I/O Register L
679
(PDIORL) (SH7149 Only)
17.1.6 Port D Control Registers L1 679
to L4 (PDCRL1 to PDCRL4)
to
(SH7149 Only)
685
Changed
Note added
Note: * This function is enabled only in the on-chip
ROM enabled/disabled external-extension
mode. Do not set 1 in single-chip mode.
Note added
Note: * This function is enabled only in the on-chip
ROM enabled/disabled external-extension
mode. Do not set 1 in single-chip mode.
Deleted
â¦. PDIORL is enabled when the port D pins are
functioning as general-purpose inputs/outputs (PD15 to
PD0), and the SCK pin is functioning as inputs/outputs
of SCI. In other states, PDIORL is disabled.
Note added
Note: * This function is enabled only in the on-chip
ROM enabled/disabled external-extension
mode. Do not set 1 in single-chip mode.
Rev. 3.00 May 17, 2007 Page 961 of 974
REJ09B0229-0300
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