SH7146 Datasheet, PDF (75/1022 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Instruction Format
nm type
15
0
xxxx nnnn mmmm xxxx
md type
15
0
xxxx xxxx mmmm dddd
nd4 type
15
0
xxxx xxxx nnnn dddd
nmd type
15
0
xxxx nnnn mmmm dddd
Section 2 CPU
Destination
Source Operand Operand
Sample Instruction
mmmm: register
direct
nnnn: register
direct
ADD Rm,Rn
mmmm: register
direct
nnnn: register
indirect
MOV.L Rm,@Rn
mmmm: post-
increment register
indirect (multiply-
and-accumulate
operation)
MACH, MACL
nnnn: * post-
increment register
indirect (multiply-
and-accumulate
operation)
MAC.W @Rm+,@Rn+
mmmm: post-
nnnn: register
increment register direct
indirect
MOV.L @Rm+,Rn
mmmm: register
direct
nnnn: pre-
MOV.L Rm,@-Rn
decrement register
indirect
mmmm: register
direct
nnnn: index
register indirect
MOV.L Rm,@(R0,Rn)
mmmmdddd:
R0 (register direct) MOV.B @(disp,Rm),R0
register indirect
with displacement
R0 (register direct) nnnndddd:
MOV.B R0,@(disp,Rn)
register indirect
with displacement
mmmm: register
direct
nnnndddd:
MOV.L Rm,@(disp,Rn)
register indirect
with displacement
mmmmdddd:
nnnn: register
register indirect direct
with displacement
MOV.L @(disp,Rm),Rn
Rev. 3.00 May 17, 2007 Page 31 of 974
REJ09B0229-0300