SH7146 Datasheet, PDF (256/1022 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
Bit
5 to 2
1, 0
Initial
Bit Name Value R/W Description

All 0
R
Reserved
HW[1:0] 00
These bits are always read as 0. The write value should
always be 0.
R/W Delay Cycles from RD and WRxx Negation to Address
and CSn Negation
Specify the number of delay cycles from RD and WRxx
negation to address and CSn negation.
00: 0.5 cycle
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
9.4.4 Bus Function Extending Register (BSCEHR)
BSCEHR is a 16-bit register that specifies the timing of bus release by the DTC. It also specifies
the application of priority in transfer operations and enables or disables the functions that have the
effect of decreasing numbers of cycles over which the DTC is active. The differences in DTC
operation made by the combinations of the DTLOCK, CSSTP1, and DTBST bits settings are
described in section 8.5.9, DTC Bus Releasing Timing.
Setting the CSSTP2 bit can improve the transfer performance of the DTC transfer when the
DTLOCK bit is 0. Furthermore, setting the CSSTP3 bit selects whether or not access to the
external space by the CPU takes priority over DTC transfer.
The DTC short address mode is implemented by setting the DTSA bit. For details of the short
address mode, see section 8.4, Location of Transfer Information and DTC Vector Table.
A DTC activation priority order can be set up for the DTC activation sources. The DTPR bit
selects whether or not this priority order is valid or invalid when multiple sources issue activation
requests before DTC activation. Do not modify this register while the DTC is active.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
DTLOCK CSSTP1 - CSSTP2 DTBST DTSA CSSTP3 DTPR
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R R/W R/W R/W R/W R/W R
R
R
R
R
R
R
R
Rev. 3.00 May 17, 2007 Page 212 of 974
REJ09B0229-0300