SH7146 Datasheet, PDF (995/1022 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Item
4.5 Changing Frequency
Table 5.5 Reset Status
Page Revision (See Manual for Details)
69 Amended
3. …..When using the MTU2S clock and MTU2 clock,
specify the frequencies to satisfy the following
condition: internal clock (Iφ) ≥ MTU2S clock (MIφ) ≥
MTU2 clock (MPφ) ≥ peripheral clock (Pφ) and bus
clock (Bφ) ≥ MTU2 clock (MPφ).
Code to rewrite values of FRQCR should be
executed in the on-chip ROM or on-chip RAM.
4. After an instruction to rewrite FRQCR has been
issued, the actual clock frequencies will change after
(1 to 24n) cyc + 11Bφ + 7Pφ.
n: Division ratio specified by the BFC bit in FRQCR
(1, 1/2, 1/3, 1/4, or 1/8)
cyc: Clock obtained by dividing EXTAL by 8 with the
PLL.
Note: (1 to 24n) depends on the internal state.
79 Amended
Internal State
Type
POE, PFC, I/O Port
Power-on reset
Initialized
Initialized
Manual reset
Not initialized
7.3.13 Branch Source Register 140
(BRSR) (F-ZTAT Version Only)
7.3.14 Branch Destination
141
Register (BRDR) (F-ZTAT Version
Only)
Amended
…. This flag bit is cleared to 0 when BRSR is read, the
setting to enable PC trace is made, or BRSR is
initialized by a power-on reset or a manual reset.
Amended
…. This flag bit is cleared to 0 when BRDR is read, the
setting to enable PC trace is made, or BRDR is
initialized by a power-on reset or a manual reset.
Rev. 3.00 May 17, 2007 Page 951 of 974
REJ09B0229-0300