SH7146 Datasheet, PDF (151/1022 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Interrupt Controller (INTC)
IRQSR.IRQnL
IRQCR.IRQn1S _IRQSR.IRQnF
IRQCR.IRQn0S
IRQn pins
Level
detection
Edge
detection
SQ
CPU interrupt
request
R
RESIRQn
(Acceptance of IRQn interrupt/
writing 0 after reading IRQnF = 1)
DTC activation
request
n = 3 to 0
Figure 6.2 Block Diagram of IRQ3 to IRQ0 Interrupts Control
6.4.2 On-Chip Peripheral Module Interrupts
On-chip peripheral module interrupts are interrupts generated by the following on-chip peripheral
modules.
Since a different interrupt vector is allocated to each interrupt source, the exception handling
routine does not have to decide which interrupt has occurred. Priority levels between 0 and 15 can
be allocated to individual on-chip peripheral modules in interrupt priority registers D to F and H to
L (IPRD to IPRF and IPRH to IPRL). On-chip peripheral module interrupt exception handling sets
the interrupt mask level bits (I3 to I0) in the status register (SR) to the priority level value of the
on-chip peripheral module interrupt that was accepted.
6.4.3 User Break Interrupt
A user break interrupt has a priority level of 15, and occurs when the break condition set in the
user break controller (UBC) is satisfied. User break interrupt requests are detected by edge and are
held until accepted. User break interrupt exception handling sets the interrupt mask level bits (I3
to I0) in the status register (SR) to level 15. For more details on the user break interrupt, see
section 7, User Break Controller (UBC).
Rev. 3.00 May 17, 2007 Page 107 of 974
REJ09B0229-0300