SH7146 Datasheet, PDF (56/1022 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 1 Overview
Classification
Bus control
Symbol
CS1, CS0
RD
WRH
WRL
WAIT
Multi function timer- TCLKA,
pulse unit 2 (MTU2) TCLKB,
TCLKC,
TCLKD
TIOC0A,
TIOC0B,
TIOC0C,
TIOC0D
TIOC1A,
TIOC1B
TIOC2A,
TIOC2B
I/O Name
Function
O Chip select 1 and Chip-select signal for external
0
memory or devices.
No chip select pins are available in
the SH7146.
O Read
Indicates reading of data from
external devices.
This pin is not available in the
SH7146.
O Write to upper Indicates a write access to bits 15 to
byte
8 of the external data.
This pin is not available in the
SH7146.
O Write to lower Indicates a write access to bits 7 to 0
byte
of the external data.
This pin is not available in the
SH7146.
I
Wait
Input signal for inserting a wait cycle
into the bus cycles during access to
the external space.
This pin is not available in the
SH7146.
I
MTU2 timer clock External clock input pins for the
input
timer.
I/O MTU2 input
capture/output
compare
(channel 0)
I/O MTU2 input
capture/output
compare
(channel 1)
I/O MTU2 input
capture/output
compare
(channel 2)
The TGRA_0 to TGRD_0 input
capture input/output compare
output/PWM output pins.
The TGRA_1 to TGRB_1 input
capture input/output compare
output/PWM output pins.
The TGRA_2 to TGRB_2 input
capture input/output compare
output/PWM output pins.
Rev. 3.00 May 17, 2007 Page 12 of 974
REJ09B0229-0300