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SH7146 Datasheet, PDF (232/1022 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family | |||
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Section 8 Data Transfer Controller (DTC)
Table 8.10 Number of Cycles Required for Each Execution State
Object to be Accessed
On-Chip
RAM*1/ROM*2
On-Chip I/O Registers
External Devices*4
Bus width
32 bits
16 bits
8 bits
16 bits
Access cycles
1BÏ to 3BÏ*1*2
2PÏ
2BÏ
2BÏ
Execu-
tion
status
Vector read SI
Transfer information read SJ
Transfer information write Sk
1BÏ to 3BÏ*1*2
1BÏ to 3BÏ*1
1BÏ to 3BÏ*1
Byte data read SL
1BÏ to 3BÏ*1
Word data read SL
1BÏ to 3BÏ*1
Longword data read SL
1BÏ to 3BÏ*1
Byte data write SM
1BÏ to 3BÏ*1
Word data write SM
1BÏ to 3BÏ*1
Longword data write SM
1BÏ to 3BÏ*1



1BÏ + 2PÏ*3
1BÏ + 2PÏ*3
1BÏ + 4PÏ*3
1BÏ + 2PÏ*3
1BÏ + 2PÏ*3
1BÏ + 4PÏ*3
9BÏ
9BÏ
2BÏ*5
3BÏ
5BÏ
9BÏ
2BÏ*5
2BÏ*5
2BÏ*5
5BÏ
5BÏ
2BÏ*5
3BÏ
3BÏ
5BÏ
2BÏ*5
2BÏ*5
2BÏ*5
Internal operation SN
1
Notes: 1. Values for on-chip RAM. Number of cycles varies depending on the ratio of IÏ:BÏ.
IÏ:BÏ = 1:1
IÏ:BÏ = 1:1/2
IÏ:BÏ = 1:1/3
IÏ:BÏ = 1:1/4 or less
Read
3BÏ
2BÏ
2BÏ
1BÏ
Write
3BÏ
1BÏ
1BÏ
1BÏ
2. Values for on-chip ROM. Number of cycles varies depending on the ratio of IÏ:BÏ.and
are the same as on-chip RAM. Only vector read is possible.
3. The values in the table are those for the fastest case. Depending on the state of the
internal bus, replace 1BÏ by 1PÏ in a slow case.
4. Values are different depending on the BSC register setting. The values in the table are
the sample for the case with no wait cycles and the WM bit in CSnWCR = 1.
5. Values are different depending on the bus state.
The number of cycles increases when many external wait cycles are inserted in the
case where writing is frequently executed, such as block transfer, and when the
external bus is in use because the write buffer cannot be used efficiently in such cases.
For details on the write buffer, see section 9.5.7 (2), Access in View of LSI Internal Bus
Master.
Rev. 3.00 May 17, 2007 Page 188 of 974
REJ09B0229-0300
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