SH7146 Datasheet, PDF(231/1022 Page) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

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SH7146 Datasheet, PDF (231/1022 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

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Section 8 Data Transfer Controller (DTC)

8.5.8 Number of DTC Execution Cycles

Table 8.9 shows the execution status for a single DTC data transfer, and table 8.10 shows the

number of cycles required for each execution.

Table 8.9 DTC Execution Status

Mode

Vector

Read

I

Transfer

Information

Read

J

Transfer

Information

Write

K

Normal 1

0*1 4 3*4 0*1 3

2*2 1*3

Repeat 1

0*1 4 3*4 0*1 3

2*2 1*3

Block

1

transfer

0*1 4 3*4 0*1 3

2*2 1*3

[Legend]

P: Block size (initial setting of CRAH and CRAL)

Notes: 1. When transfer information read is skipped

2. When the SAR or DAR is in fixed mode

3. When the SAR and DAR are in fixed mode

4. When short address mode

Data Read

L

Data

Write

M

1

1

1

1

1â¢P

1â¢P

Internal

Operation

N

1

0*1

1

0*1

1

0*1

Rev. 3.00 May 17, 2007 Page 187 of 974

REJ09B0229-0300

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