SH7146 Datasheet, PDF (266/1022 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
9.5.3 Access Wait Control
Wait cycle insertion on a normal space access can be controlled by the settings of bits WR3 to
WR0 in CSnWCR. It is possible to insert wait cycles independently in read access and in write
access. The specified number of Tw cycles is inserted as wait cycles in a normal space access
shown in figure 9.7.
T1
Tw
T2
CK
A19 to A0
CSn
Read
RD
D15 to D0
Write
WRxx
D15 to D0
Figure 9.7 Wait Timing for Normal Space Access (Software Wait Only)
Rev. 3.00 May 17, 2007 Page 222 of 974
REJ09B0229-0300