SH7146 Datasheet, PDF (552/1022 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 12 Port Output Enable (POE)
Initial
Bit
Bit Name value R/W Description
7 to 0 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
2. Can be modified only once after a power-on reset.
12.3.5 Input Level Control/Status Register 3 (ICSR3)
ICSR3 is a 16-bit readable/writable register that selects the POE8 pin input mode, controls the
enable/disable of interrupts, and indicates status.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
- POE8F -
- POE8E PIE3
-
-
-
-
-
-
POE8M[1:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R R/(W)*¹ R
R R/W*² R/W R
R
R
R
R
R R/W*² R/W*²
Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
2. Can be modified only once after a power-on reset.
Bit
15 to
13
12
Bit Name
—
POE8F
Initial
value
All 0
0
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/(W)*¹ POE8 Flag
This flag indicates that a high impedance request has
been input to the POE8 pin.
[Clearing conditions]
• By writing 0 to POE8F after reading POE8F = 1
(when the falling edge is selected by bits 1 and 0 in
ICSR3)
• By writing 0 to POE8F after reading POE8F = 1 after
a high level input to POE8 is sampled at Pφ/8, Pφ/16,
or Pφ/128 clock (when low-level sampling is selected
by bits 1 and 0 in ICSR3)
[Setting condition]
• When the input condition set by bits 1 and 0 in
ICSR3 occurs at the POE8 pin
Rev. 3.00 May 17, 2007 Page 508 of 974
REJ09B0229-0300