SH7146 Datasheet, PDF (715/1022 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 17 Pin Function Controller (PFC)
17.1.3 Port B I/O Register L, H (PBIORL, PBIORH)
PBIORL and PBIORH are 16-bit readable/writable registers that are used to set the pins on port B
as inputs or outputs. Bits PB18IOR to PB16IOR and PB5IOR to PB0IOR correspond to pins PB18
to PB16 and PB5 to PB0, respectively (names of multiplexed pins are here given as port names
and pin numbers alone). PBIORL is enabled when the port B pins are functioning as general-
purpose inputs/outputs (PB5 to PB0). In other states, PBIORL is disabled. PBIORH is enabled
when the port B pins are functioning as general-purpose inputs/outputs (PB18 to PB16). In other
states, PBIORH is disabled.
A given pin on port B will be an output pin if the corresponding bit in PBIORH or PBIORL is set
to 1, and an input pin if the bit is cleared to 0.
However, bits 1 and 0 of PBIORL are disabled in SH7146.
Bits 15 to 6 of PBIORL and bits 15 to 3 of PBIORH are reserved. These bits are always read as 0.
The write value should always be 0.
The initial value of PBIORL and PBIORH are H'0000, respectively.
• Port B I/O Register H (PBIORH)
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
-
PB18 PB17 PB16
IOR IOR IOR
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R R/W R/W R/W
• Port B I/O Register L (PBIORL)
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
PB5 PB4 PB3 PB2 PB1 PB0
IOR IOR IOR IOR IOR IOR
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R R/W R/W R/W R/W R/W R/W
Rev. 3.00 May 17, 2007 Page 671 of 974
REJ09B0229-0300