SH7146 Datasheet, PDF (177/1022 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 7 User Break Controller (UBC)
Initial
Bit
Bit Name Value R/W Description
5
IDB1*
0
R/W Instruction Fetch/Data Access Select B
4
IDB0
0
R/W Select the instruction fetch cycle or data access cycle
as the bus cycle of the channel B break condition.
00: Condition comparison is not performed
01: The break condition is the instruction fetch cycle
10: The break condition is the data access cycle
11: The break condition is the instruction fetch cycle or
data access cycle
3
RWB1* 0
R/W Read/Write Select B
2
RWB0
0
R/W Select the read cycle or write cycle as the bus cycle of
the channel B break condition.
00: Condition comparison is not performed
01: The break condition is the read cycle
10: The break condition is the write cycle
11: The break condition is the read cycle or write cycle
1
SZB1*
0
R/W Operand Size Select B
0
SZB0*
0
R/W Select the operand size of the bus cycle for the
channel B break condition.
00: The break condition does not include operand size
01: The break condition is byte access
10: The break condition is word access
11: The break condition is longword access
Note: When specifying the operand size, specify the
size which matches the address boundary.
[Legend]
x:
Don't care.
Note: * In the masked ROM version, these bits are reserved bits. They are always read as 0,
and the write value should always be 0.
Rev. 3.00 May 17, 2007 Page 133 of 974
REJ09B0229-0300