SH7146 Datasheet, PDF (51/1022 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

1.3 Pin Assignments
Section 1 Overview
PB3/IRQ1/POE1/TIC5V
PB2/IRQ0/POE0/TIC5VS
AVSS
PF15/AN15
PF14/AN14
PF13/AN13
PF12/AN12
PF11/AN11
PF10/AN10
PF9/AN9
PF8/AN8
AVCC
PF6/AN6
PF4/AN4
AVSS
PF2/AN2
PF0/AN0
AVCC
PB16/POE3
PB17/POE7
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
61
40
62
39
63
38
64
37
65
36
66
35
67
34
68
33
69
32
70
LQFP-80
31
71
(Top view)
30
72
29
73
28
74
27
75
26
76
25
77
24
78
23
79
22
80
21
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
PA6/UBCTRG/TCLKA/POE4
PA7/TCLKB/POE5/SCK2
PA8/TCLKC/POE6/RXD2
PA9/TCLKD/POE8/TXD2
PA10/RXD0
PA11/TXD0/ADTRG
PA12/SCK0
VSS
PA13/SCK1
VCC
PA14/RXD1
PA15/TXD1
PB18/POE8
PE0/TIOC0A
PE1/TIOC0B/RXD0
PE2/TIOC0C/TXD0
PE3/TIOC0D/SCK0
PE4/TIOC1A/RXD1
PE5/TIOC1B/TXD1
PE6/TIOC2A/SCK1
Notes: 1. Fixed to VSS in the masked ROM version, and used as the FWE input pin in the F-ZTAT version.
2. A pin for the E10A emulator. Fixed to VCC in the masked ROM version, and used as the ASEMD0 input pin in the F-ZTAT version.
3. This pin function is available only in the F-ZTAT version. (Not available in the masked ROM version.)
Figure 1.2 Pin Assignments of SH7146
Rev. 3.00 May 17, 2007 Page 7 of 974
REJ09B0229-0300