SH7146 Datasheet, PDF (267/1022 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
When the WM bit in CSnWCR is cleared to 0, the external wait input WAIT signal is also
sampled. WAIT pin sampling is shown in figure 9.8. A 2-cycle wait is specified as a software
wait. The WAIT signal is sampled at the falling edge of CK at the transition from the T1 or Tw
cycle to the T2 cycle.
Wait states inserted
by WAIT signal
T1
Tw
Tw
Twx
T2
CK
A19 to A0
CSn
Read
RD
D15 to D0
Write
WRxx
D15 to D0
WAIT
Figure 9.8 Wait State Timing for Normal Space Access
(Wait State Insertion Using WAIT Signal)
Rev. 3.00 May 17, 2007 Page 223 of 974
REJ09B0229-0300