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SH7146 Datasheet, PDF (673/1022 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family | |||
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Section 16 Compare Match Timer (CMT)
Section 16 Compare Match Timer (CMT)
This LSI has an on-chip compare match timer (CMT) consisting of a 2-channel 16-bit timer. The
CMT has a16-bit counter, and can generate interrupts at set intervals.
16.1 Features
⢠Selection of four counter input clocks
Any of four internal clocks (PÏ/8, PÏ/32, PÏ/128, and PÏ/512) can be selected independently
for each channel.
⢠Interrupt request on compare match
⢠Module standby mode can be set.
Figure 16.1 shows a block diagram of CMT.
CMI0
PÏ/32
PÏ/512
PÏ/8
PÏ/128
Control circuit
Clock selection
CMI1
PÏ/32
PÏ/512
PÏ/8
PÏ/128
Control circuit
Clock selection
Channel 0
Module bus
[Legend]
CMSTR:
CMCSR:
CMCOR:
CMCNT:
CMI:
CMT
Compare match timer start register
Compare match timer control/status register
Compare match timer constant register
Compare match counter
Compare match interrupt
Figure 16.1 Block Diagram of CMT
Channel 1
Bus
interface
Internal bus
TIMCMT3A_000020030900
Rev. 3.00 May 17, 2007 Page 629 of 974
REJ09B0229-0300
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