SH7146 Datasheet, PDF (97/1022 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 3 MCU Operating Modes
H'00000000
H'000FFFFF
H'00100000
Modes 0 and 1
On-chip ROM disabled mode
CS0 space
Reserved area
H'03FFFFFF
H'04000000
H'040FFFFF
H'04100000
CS1 space
H'00000000
Mode 2
On-chip ROM enabled mode
H'0003FFFF
H'00040000
H'01FFFFFF
H'02000000
H'020FFFFF
H'02100000
H'03FFFFFF
H'04000000
H'040FFFFF
H'04100000
On-chip ROM (256 kbytes)
Reserved area
CS0 space
Reserved area
CS1 space
H'00000000
H'0003FFFF
H'00040000
Mode 3
Single chip mode
On-chip ROM (256 kbytes)
Reserved area
Reserved area
Reserved area
H'FFFF8FFF
H'FFFF9000
H'FFFF8FFF
H'FFFF9000
H'FFFF8FFF
H'FFFF9000
On-chip RAM (8 kbytes)
On-chip RAM (8 kbytes)
On-chip RAM (8 kbytes)
H'FFFFAFFF
H'FFFFB000
H'FFFFBFFF
H'FFFFC000
H'FFFFFFFF
Reserved area
On-chip peripheral
I/O registers
H'FFFFAFFF
H'FFFFB000
H'FFFFBFFF
H'FFFFC000
H'FFFFFFFF
Reserved area
On-chip peripheral
I/O registers
H'FFFFAFFF
H'FFFFB000
H'FFFFBFFF
H'FFFFC000
H'FFFFFFFF
Reserved area
On-chip peripheral
I/O registers
Figure 3.2 Address Map for Each Operating Mode in SH7149
Rev. 3.00 May 17, 2007 Page 53 of 974
REJ09B0229-0300