SH7146 Datasheet, PDF (257/1022 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
15
DTLOCK 0
R/W DTC Lock Enable
Specifies the timing of bus release by the DTC.
0: The DTC releases the bus on generation of the NOP
cycle that follows vector read or write-back of transfer
information.
1: The DTC releases the bus after vector read, on
generation of the NOP cycle that follows vector read,
after transfer information read, after a round of data
transfer, or after write-back of transfer information.
14
CSSTP1 0
R/W Select Bus Release on NOP Cycle Generation by DTC
Specifies whether or not the bus is released in response
to requests from the CPU for external space access on
generation of the NOP cycle that follows reading of the
vector address.
If, however, the CSSTP2 bit is 1, bus mastership is
retained until all transfer is complete, regardless of the
setting of this bit.
0: The bus is released on generation of the NOP cycle by
the DTC.
1: The bus is not released on generation of the NOP
cycle by the DTC.
13

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
12
CSSTP2 0
R/W Select Bus Release during DTC Transfer
This setting applies to DTC transfer when the DTLOCK
bit is 0. The value specifies whether the bus mastership
is or is not to be released after each round of transfer in
response to a request from the CPU for access to the
external space.
0: When the DTLOCK and CSSTP1 bits are 0, the bus is
released on generation of the NOP cycle after reading
of the vector address. When the DTLOCK bit is 0 and
the CSSTP1 bit is 1, the bus is released after each
round of data transfer.
1: Only release the bus mastership after all data transfer
is complete.
Rev. 3.00 May 17, 2007 Page 213 of 974
REJ09B0229-0300