SH7146 Datasheet, PDF(215/1022 Page) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

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SH7146 Datasheet, PDF (215/1022 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

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Section 8 Data Transfer Controller (DTC)

Origin of

Activation

Source

Activation

Source

DTC Vector

Vector Address

Number Offset

DTCE*1

Transfer

Source

Transfer

Destination Priority

MTU2S_3 TGIA_3S 160

H'680

DTCERC3 Arbitrary*2 Arbitrary*2 High

TGIB_3S 161

H'684

DTCERC2 Arbitrary*2 Arbitrary*2

TGIC_3S 162

H'688

DTCERC1 Arbitrary*2 Arbitrary*2

TGID_3S 163

H'68C

DTCERC0 Arbitrary*2 Arbitrary*2

MTU2S_4 TGIA_4S 168

H'6A0

DTCERD15 Arbitrary*2 Arbitrary*2

TGIB_4S 169

H'6A4

DTCERD14 Arbitrary*2 Arbitrary*2

TGIC_4S 170

H'6A8

DTCERD13 Arbitrary*2 Arbitrary*2

TGID_4S 171

H'6AC

DTCERD12 Arbitrary*2 Arbitrary*2

TCIV_4S 172

H'6B0

DTCERD11 Arbitrary*2 Arbitrary*2

MTU2S_5 TGIU_5S 176

H'6C0

DTCERD10 Arbitrary*2 Arbitrary*2

TGIV_5S 177

H'6C4

DTCERD9 Arbitrary*2 Arbitrary*2

TGIW_5S 178

H'6C8

DTCERD8 Arbitrary*2 Arbitrary*2

CMT_0

CMI_0

184

H'6E0

DTCERD7 Arbitrary*2 Arbitrary*2

CMT_1

CMI_1

188

H'6F0

DTCERD6 Arbitrary*2 Arbitrary*2

A/D_0, A/D_1 ADI_0

200

H'720

DTCERD5 ADDR0 to Arbitrary*2

ADDR3

ADI_1

201

H'724

DTCERD4 ADDR4 to Arbitrary*2

ADDR7

A/D_2

ADI_2

204

H'730

DTCERD3 ADDR8 to Arbitrary*2

ADDR15

SCI_0

RXI_0

217

H'764

DTCERE15 SCRDR_0 Arbitrary*2

TXI_0

218

H'768

DTCERE14 Arbitrary*2 SCTDR_0

SCI_1

RXI_1

221

H'774

DTCERE13 SCRDR_1 Arbitrary*2

TXI_1

222

H'778

DTCERE12 Arbitrary*2 SCTDR_1

SCI_2

RXI_2

225

H'784

DTCERE11 SCRDR_2 Arbitrary*2

TXI_2

226

H'788

DTCERE10 Arbitrary*2 SCTDR_2 Low

Notes: 1. The DTCE bits with no corresponding interrupt are reserved, and the write value should

always be 0. To leave software standby mode with an interrupt, write 0 to the

corresponding DTCE bit.

2. An external memory, a memory-mapped external device, an on-chip memory, or an on-

chip peripheral module (except DTC, BSC, UBC, and FLASH) can be selected as the

source or destination. Note that at least either the source or destination must be an on-

chip peripheral module; transfer cannot be done among an external memory, a

memory-mapped external device, and an on-chip memory.

Rev. 3.00 May 17, 2007 Page 171 of 974

REJ09B0229-0300

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