SH7146 Datasheet, PDF (251/1022 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
9.4.2 CSn Space Bus Control Register (CSnBCR) (n = 0 and 1)
CSnBCR is a 32-bit readable/writable register that specifies the data bus width of the respective
space, and the number of wait cycles between access cycles.
Do not access external memory other than area 0 until the register initialization is complete.
Bit: 31
-
Initial value: 0
R/W: R
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
IWW[1:0]
-
IWRWD[1:0]
-
IWRWS[1:0]
-
IWRRD[1:0]
-
IWRRS[1:0]
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
R R/W R/W R R/W R/W R R/W R/W R R/W R/W R R/W R/W
Bit name: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
BSZ[1:0]
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0 1* 1* 0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R R/W R/W R
R
R
R
R
R
R
R
R
Note: * When the on-chip ROM is disabled, CS0BCR samples the value input through the MD0 and MD1 external pins that
specify the bus width when a power-on reset is performed.
Initial
Bit
Bit Name Value R/W
31, 30 
All 0 R
29, 28 IWW[1:0] 11
R/W
27

0
R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Specification for Idle Cycles between Write-Read/Write-
Write Cycles
Specify the number of idle cycles to be inserted after
access to memory that is connected to the space. The
target cycles are write-read cycles and write-write
cycles.
00: No idle cycle inserted
01: 1 idle cycle inserted
10: 2 idle cycles inserted
11: 4 idle cycles inserted
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 3.00 May 17, 2007 Page 207 of 974
REJ09B0229-0300