SH7146 Datasheet, PDF (644/1022 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 15 A/D Converter (ADC)
Figure 15.1 shows a block diagram of the A/D converter.
Module data bus
Internal data bus
AV_CC
AV_SS
10-bit D/A
ANm
•
•
•
•
•
•
ANn
+
Comparator
Sample-and-
hold circuit
Control circuit
Pφ
Pφ/2
Pφ/3
Pφ/4
ADI
interrupt signal
Conversion start
trigger from MTU2/MTU2S
ADTRG
[Legend]
ADCR:
A/D control register
ADCSR:
A/D control/status register
ADTSR:
A/D trigger select register
ADDRm to ADDRn: A/D data registers m to n
Note: The register number corresponds to the channel number of the module.
(m to n = 0, 2, 4, 6, and 8 to 15)
Figure 15.1 Block Diagram of A/D Converter (for One Module)
Rev. 3.00 May 17, 2007 Page 600 of 974
REJ09B0229-0300