SH7146 Datasheet, PDF (50/1022 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 1 Overview
1.2 Block Diagram
The block diagram of this LSI is shown in figure 1.1.
SH2
CPU
UBC
AUD
*²
L bus (Iφ)
ROM
RAM
Internal bus
controller
I bus (Bφ)
BSC
Peripheral bus
controller
DTC
*¹
External bus
Peripheral bus (Pφ)
I/O
port
(PFC)
SCI CMT H-UDI INTC Power- WDT CPG MTU2 MTU2S POE ADC
*¹
down
mode
control
[Legend]
ROM:
RAM:
UBC:
AUD:
H-UDI:
INTC:
CPG:
WDT:
CPU:
BSC:
On-chip ROM
On-chip RAM
User break controller
Advanced user debugger
User debugging interface
Interrupt controller
Clock pulse generator
Watchdog timer
Central processing unit
Bus state controller
DTC: Data transfer controller
PFC: Pin function controller
MTU2: Multi-function timer pulse unit 2
MTU2S: Multi-function timer pulse unit 2 (subset)
POE: Port output enable
SCI: Serial communication interface
CMT: Compare match timer
ADC: A/D converter
Notes: 1. Only in F-ZTAT version.
2. Only in F-ZTAT version supporting full functions of E10A.
Figure 1.1 Block Diagram
Rev. 3.00 May 17, 2007 Page 6 of 974
REJ09B0229-0300