SH7146 Datasheet, PDF (25/1022 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Figures
Section 1 Overview
Figure 1.1 Block Diagram .............................................................................................................. 6
Figure 1.2 Pin Assignments of SH7146.......................................................................................... 7
Figure 1.3 Pin Assignments of SH7149 (LQFP Version)............................................................... 8
Figure 1.4 Pin Assignments of SH7149 (QFP Version) ................................................................. 9
Section 2 CPU
Figure 2.1 CPU Internal Register Configuration .......................................................................... 18
Figure 2.2 Register Data Format................................................................................................... 22
Figure 2.3 Memory Data Format .................................................................................................. 22
Figure 2.4 Transitions between Processing States ........................................................................ 46
Section 3 MCU Operating Modes
Figure 3.1 Address Map for Each Operating Mode in SH7146.................................................... 52
Figure 3.2 Address Map for Each Operating Mode in SH7149.................................................... 53
Figure 3.3 Reset Input Timing when Changing Operating Mode................................................. 54
Section 4 Clock Pulse Generator (CPG)
Figure 4.1 Block Diagram of Clock Pulse Generator ................................................................... 56
Figure 4.2 Connection of Crystal Resonator (Example)............................................................... 70
Figure 4.3 Crystal Resonator Equivalent Circuit .......................................................................... 70
Figure 4.4 Example of External Clock Connection ...................................................................... 71
Figure 4.5 Cautions for Oscillator Circuit Board Design ............................................................. 73
Figure 4.6 Recommended External Circuitry around PLL ........................................................... 74
Section 6 Interrupt Controller (INTC)
Figure 6.1 Block Diagram of INTC.............................................................................................. 94
Figure 6.2 Block Diagram of IRQ3 to IRQ0 Interrupts Control................................................. 107
Figure 6.3 Interrupt Sequence Flowchart.................................................................................... 113
Figure 6.4 Stack after Interrupt Exception Handling .................................................................. 114
Figure 6.5 IRQ Interrupt Control Block Diagram....................................................................... 116
Figure 6.6 On-Chip Module Interrupt Control Block Diagram .................................................. 117
Section 7 User Break Controller (UBC)
Figure 7.1 Block Diagram of UBC............................................................................................. 120
Section 8 Data Transfer Controller (DTC)
Figure 8.1 Block Diagram of DTC ............................................................................................. 156
Figure 8.2 Transfer Information on Data Area ........................................................................... 169
Figure 8.3 Correspondence between DTC Vector Address and Transfer Information............... 169
Rev. 3.00 May 17, 2007 Page xxv of xliv