SH7146 Datasheet, PDF (1013/1022 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Index
A
A/D conversion time............................... 619
A/D converter (ADC) ............................. 599
A/D converter activation......................... 422
A/D converter characteristics.................. 931
A/D converter interrupt source ............... 622
A/D converter start request delaying
function................................................... 405
Absolute accuracy................................... 623
Absolute maximum ratings..................... 903
AC bus timing......................................... 914
AC characteristics................................... 907
AC characteristics measurement
conditions ............................................... 930
Access in view of LSI
internal bus master.................................. 232
Access size and data alignment .............. 216
Access wait control................................. 222
Address error .............................. 81, 90, 842
Address map ........................................... 201
Addressing modes..................................... 26
Arithmetic operation instructions ............. 39
Asynchronous mode ....................... 533, 566
C
Calculating exception handling
vector table addresses ............................... 78
Chain transfer.......................................... 182
Changing frequency .................................. 69
Clock (MIφ) for the MTU2S module ........ 55
Clock (MPφ) for the MTU2 module ......... 55
Clock frequency control circuit................. 57
Clock operating mode ............................... 60
Clock pulse generator (CPG) .................... 55
Clock synchronous mode ................ 533, 576
Clock timing ........................................... 908
CMT interrupt sources ............................ 635
Compare match timer (CMT) ................. 629
Complementary PWM mode .................. 361
Conflict between NMI interrupt
and DTC activation ................................. 197
Connecting crystal resonator..................... 70
Continuous scan mode ............................ 616
Control signal timing .............................. 911
CPU........................................................... 17
Crystal oscillator ....................................... 57
CSn assert period extension .................... 224
B
Block transfer mode................................ 181
Boot mode .............................................. 770
Branch instructions ................................... 43
Break comparison conditions ................. 119
Break detection and processing .............. 595
Break on data access cycle ..................... 144
Break on instruction fetch cycle ............. 143
Bus arbitration ........................................ 228
Bus clock (Bφ) .......................................... 55
Bus release state........................................ 47
Bus state controller (BSC) ...................... 199
D
Data transfer controller (DTC)................ 155
Data transfer instructions .......................... 37
DC characteristics ................................... 904
Dead time compensation......................... 416
Deep software standby mode .................. 857
Divider ...................................................... 57
DTC activation........................................ 421
DTC activation by interrupt .................... 193
DTC activation sources........................... 168
DTC bus release timing .......................... 189
DTC execution status.............................. 187
Rev. 3.00 May 17, 2007 Page 969 of 974
REJ09B0229-0300