SH7146 Datasheet, PDF (883/1022 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 20 Masked ROM
Section 20 Masked ROM
This LSI is available with 256 kbytes of on-chip masked ROM. The on-chip ROM is connected to
the CPU and data transfer controller (DTC) through a 32-bit data bus (figure 20.1). The CPU and
DTC can access the on-chip ROM in 8, 16, and 32-bit widths. Data in the on-chip ROM can
always be accessed from the CPU in one cycle.
Internal data bus (32 bits)
H'00000000
H'00000004
H'00000001
H'00000005
H'00000002
H'00000006
H'00000003
H'00000007
On-chip ROM
H'0003FFFC
H'0003FFFD
H'0003FFFE
H'0003FFFF
Figure 20.1 Masked ROM Block Diagram
The operating mode determines whether the on-chip ROM is valid or not. The operating mode is
selected using mode-setting pins FWE, MD1, and MD0. If you are using the on-chip ROM, select
mode 2 or mode 3; if you are not, select mode 0 or 1. The on-chip ROM is allocated to addresses
H'00000000 to H'0003FFFF of memory area 0.
Rev. 3.00 May 17, 2007 Page 839 of 974
REJ09B0229-0300