SH7146 Datasheet, PDF (147/1022 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Interrupt Controller (INTC)
Initial
Bit
Bit Name Value
R/W Description
0
IRQ0F
0
R/W Indicates the status of an IRQ0 interrupt request.
• When level detection mode is selected
0: An IRQ0 interrupt has not been detected
[Clearing condition]
Driving pin IRQ0 high
1: An IRQ0 interrupt has been detected
[Setting condition]
Driving pin IRQ0 low
• When edge detection mode is selected
0: An IRQ0 interrupt has not been detected
[Clearing conditions]
 Writing 0 after reading IRQ0F = 1
 Accepting an IRQ0 interrupt
1: An IRQ0 interrupt request has been detected
[Setting condition]
Detecting the specified edge of pin IRQ0
Note: * The initial value is 1 when the level on the corresponding IRQ pin is high, and 0 when
the level on the pin is low.
6.3.4
Interrupt Priority Registers A, D to F, and H to L (IPRA, IPRD to IPRF, and
IPRH to IPRL)
Interrupt priority registers are nine 16-bit readable/writable registers that set priority levels from 0
to 15 for interrupts except NMI. For the correspondence between interrupt request sources and
IPR, refer to table 6.3. Each of the corresponding interrupt priority ranks are established by setting
a value from H'0 to H'F in each of the four-bit groups 15 to 12, 11 to 8, 7 to 4 and 3 to 0. Reserved
bits that are not assigned should be set H'0 (B'0000).
Bit: 15
Initial value: 0
R/W: R/W
14 13
IPR[15:12]
0
0
R/W R/W
12
0
R/W
11
0
R/W
10 9
IPR[11:8]
0
0
R/W R/W
8
0
R/W
7
0
R/W
6
5
IPR[7:4]
0
0
R/W R/W
4
0
R/W
3
0
R/W
2
1
IPR[3:0]
0
0
R/W R/W
0
0
R/W
Rev. 3.00 May 17, 2007 Page 103 of 974
REJ09B0229-0300