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SH7146 Datasheet, PDF (214/1022 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family
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Section 8 Data Transfer Controller (DTC)
Table 8.2 shows correspondence between the DTC activation source and vector address.
Table 8.2 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs
Origin of
Activation
Source
External pin
MTU2_0
MTU2_1
MTU2_2
MTU2_3
MTU2_4
MTU2_5
Activation
Source
IRQ0
IRQ1
IRQ2
IRQ3
TGIA_0
TGIB_0
TGIC_0
TGID_0
TGIA_1
TGIB_1
TGIA_2
TGIB_2
TGIA_3
TGIB_3
TGIC_3
TGID_3
TGIA_4
TGIB_4
TGIC_4
TGID_4
TCIV_4
TGIU_5
TGIV_5
TGIW_5
Vector
Number
64
65
66
67
88
89
90
91
96
97
104
105
112
113
114
115
120
121
122
123
124
128
129
130
DTC Vector
Address
Offset
DTCE*1
H'500
DTCERA15
H'504
DTCERA14
H'508
DTCERA13
H'50C
DTCERA12
H'560
DTCERB15
H'564
DTCERB14
H'568
DTCERB13
H'56C
DTCERB12
H'580
DTCERB11
H'584
DTCERB10
H'5A0
DTCERB9
H'5A4
DTCERB8
H'5C0
DTCERB7
H'5C4
DTCERB6
H'5C8
DTCERB5
H'5CC
DTCERB4
H'5E0
DTCERB3
H'5E4
DTCERB2
H'5E8
DTCERB1
H'5EC
DTCERB0
H'5F0
DTCERC15
H'600
DTCERC14
H'604
DTCERC13
H'608
DTCERC12
Transfer
Source
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Transfer
Destination
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Arbitrary*2
Priority
High
Low
Rev. 3.00 May 17, 2007 Page 170 of 974
REJ09B0229-0300
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