SH7146 Datasheet, PDF (836/1022 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 19 Flash Memory
H'00000
H'01000
H'02000
H'03000
H'04000
H'05000
H'06000
H'07000
H'08000
EB0
EB1
EB2
EB3
EB4
EB5
EB6
EB7
Flash memory
(user MAT)
EB8 to EB11
This area is accessible as both a RAM
area and as a flash memory area.
H'FFFF9000
On-chip RAM
H'FFFF9FFF
H'FFFFA000
H'FFFFAFFF
H'3FFFF
Figure 19.17 Example of Overlapped RAM Operation
Figure 19.17 shows an example of an overlap on block area EB0 of the flash memory.
Emulation is possible for a single area selected from among the eight areas, from EB0 to EB7, of
the user MAT. The area is selected by the setting of the RAM2 to RAM0 bits in RAMER.
1. To overlap a part of the RAM on area EB0, to allow realtime programming of the data for this
area, set the RAMS bit in RAMER to 1, and each of the RAM2 to RAM0 bits to 0.
2. Realtime programming is carried out using the overlaid area of RAM.
In programming or erasing the user MAT, it is necessary to run a program that implements a series
of procedural steps, including the downloading of an on-chip program. In this process, set the
download area with FTDAR so that the overlaid RAM area and the area where the on-chip
program is to be downloaded do not overlap.
Figure 19.18 shows an example of programming data that has been emulated to the EB0 area in
the user MAT.
Rev. 3.00 May 17, 2007 Page 792 of 974
REJ09B0229-0300