SH7146 Datasheet, PDF (244/1022 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
Figure 9.1 shows a block diagram of the BSC.
BACK
BREQ
WAIT
CS0, CS1
A19 to A0,
D15 to D0
RD, WRH, WRL
Bus
mastership
controller
Wait
controller
Area
controller
Memory
controller
CMNCR
CS0WCR
CS1WCR
CS0BCR
CS1BCR
[Legend]
CMNCR:
CSnWCR:
CSnBCR:
Common control register
CSn space wait control register (n = 0 and 1)
CSn space bus control register (n = 0 and 1)
BSC
Figure 9.1 Block Diagram of BSC
Internal master
module
Internal slave
module
Rev. 3.00 May 17, 2007 Page 200 of 974
REJ09B0229-0300