SH7146 Datasheet, PDF (899/1022 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 22 Power-Down Modes
22.5 Software Standby Mode
22.5.1 Transition to Software Standby Mode
This LSI switches from a program execution state to software standby mode by executing the
SLEEP instruction when the STBY bit in STBCR1 and the STBYMD bit in STBCR6 are set to 1.
However, software standby mode cannot be entered when the bus is released (low-level input to
BREQ pin). Execute the SLEEP instruction after halting the DTC. In software standby mode, not
only the CPU but also the clock and on-chip peripheral modules halt.
The contents of the CPU registers and the data of the on-chip RAM remain unchanged. Some
registers of on-chip peripheral modules are, however, initialized. For details on the states of on-
chip peripheral module registers in software standby mode, refer to section 23.3, Register States in
Each Operating Mode. For details on the pin states in software standby mode, refer to appendix A,
Pin States.
The procedure for switching to software standby mode is as follows:
1. Clear the TME bit in the timer control register (WTCSR) of the WDT to 0 to stop the WDT.
2. Set the timer counter (WTCNT) of the WDT to 0 and bits CKS2 to CKS0 in WTCSR to
appropriate values to secure the specified oscillation settling time.
3. If the DTC is operating, stop its operation.
4. If the bus is released (low-level input to BREQ pin), acquire the bus mastership (high-level
input to BREQ pin).
5. After setting the STBY bit in STBCR1 and the STBYMD bit in STBCR6 to 1, execute the
SLEEP instruction.
6. Software standby mode is entered and the clocks within this LSI are halted.
Rev. 3.00 May 17, 2007 Page 855 of 974
REJ09B0229-0300