HD64F2636F20 Datasheet, PDF (995/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 23A Power-Down Modes [HD64F2636F, HD64F2638F, HD6432636F,
HD6432638F, HD64F2630F, HD6432630F, HD64F2635F, HD6432635F, HD6432634F]
23A.8 φ Clock Output Disabling Function
Output of the φ clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the
corresponding port. When the PSTOP bit is set to 1, the φ clock stops at the end of the bus cycle,
and φ output goes high. φ clock output is enabled when the PSTOP bit is cleared to 0. When DDR
for the corresponding port is cleared to 0, φ clock output is disabled and input port mode is set.
Table 23A-6 shows the state of the φ pin in each processing state.
Using the on-chip PLL circuit to lower the oscillator frequency or prohibiting external φ clock
output also have the effect of reducing unwanted electromagnetic interference*. Therefore,
consideration should be given to these options when deciding on system board settings.
Note: * Electromagnetic interference: EMI (Electro Magnetic Interference)
Table 23A-6 φ Pin State in Each Processing State
DDR
PSTOP
Hardware standby mode
Software standby
Sleep mode
High-speed mode, medium-speed
mode
0
—
High impedance
High impedance
High impedance
High impedance
1
0
High impedance
Fixed high
φ output
φ output
1
1
High impedance
Fixed high
Fixed high
Fixed high
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 945 of 1458