HD64F2636F20 Datasheet, PDF (212/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 7 Bus Controller
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Bit 3 Bit 2 Bit 1 Bit 0
AE3 AE2 AE1 AE0 Description
0
0
0
0
A8 to A23 address output disabled
(Initial value^*)
1
A8 address output enabled; A9 to A23 address output disabled
1
0
A8, A9 address output enabled; A10 to A23 address output
disabled
1
A8 to A10 address output enabled; A11 to A23 address output
disabled
1
0
0
A8 to A11 address output enabled; A12 to A23 address output
disabled
1
A8 to A12 address output enabled; A13 to A23 address output
disabled
1
0
A8 to A13 address output enabled; A14 to A23 address output
disabled
1
A8 to A14 address output enabled; A15 to A23 address output
disabled
1
0
0
0
A8 to A15 address output enabled; A16 to A23 address output
disabled
1
A8 to A16 address output enabled; A17 to A23 address output
disabled
1
0
A8 to A17 address output enabled; A18 to A23 address output
disabled
1
A8 to A18 address output enabled; A19 to A23 address output
disabled
1
0
0
A8 to A19 address output enabled; A20 to A23 address output
disabled
1
A8 to A20 address output enabled; A21 to A23 address output
disabled
(Initial value^*)
1
0
A8 to A21 address output enabled; A22, A23 address output
disabled
1
A8 to A23 address output enabled
Note: * In on-chip ROM-enabled expansion mode, bits AE3 to AE0 are initialized to B'0000.
In on-chip ROM-disabled expansion mode, bits AE3 to AE0 are initialized to B'1101.
Address pins A0 to A7 are made address outputs by setting the corresponding DDR bits to
1.
Page 162 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010