HD64F2636F20 Datasheet, PDF (1405/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Appendix B Internal I/O Register
TSYR—Timer Synchro Register
H'FEB1
TPU
Bit
7
⎯
Initial value
0
Read/Write
⎯
6
5
4
3
2
1
0
⎯ SYNC5 SYNC4 SYNC3 SYNC2 SYNC1 SYNC0
0
0
0
0
0
0
0
⎯
R/W R/W R/W R/W R/W R/W
Timer Synchro
0 TCNTn operates independently (TCNT presetting/
clearing is unrelated to other channels)
1 TCNTn performs synchronous operation
TCNT synchronous presetting/synchronous clearing
is possible
(n = 5 to 0)
Notes: 1. To set synchronous operation, the SYNC bits for at least two channels must be set to 1.
2. To set synchronous clearing, in addition to the SYNC bit , the TCNT clearing source
must also be set by means of bits CCLR2 to CCLR0 in TCR.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 1355 of 1458