HD64F2636F20 Datasheet, PDF (872/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 21B ROM
(H8S/2638 Group, H8S/2639 Group, H8S/2630 Group)
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
and TE bits in SCR to 0), but the adjusted bit rate value remains set in BRR. The transmit data
output pin, TxD1, goes to the high-level output state (P33DDR = 1, P33DR = 1).
The contents of the CPU’s internal general registers are undefined at this time, so these
registers must be initialized immediately after branching to the programming control program.
In particular, since the stack pointer (SP) is used implicitly in subroutine calls, etc., a stack area
must be specified for use by the programming control program.
The initial values of other on-chip registers are not changed.
• Boot mode can be entered by making the pin settings shown in table 21B-9 and executing a
reset-start.
Boot mode can be cleared by driving the reset pin low, waiting at least 20 states, then setting
the FWE pin and mode pins, and executing reset release*¹. Boot mode can also be cleared by a
WDT overflow reset.
Do not change the mode pin input levels in boot mode, and do not drive the FWE pin low
while the boot program is being executed or while flash memory is being programmed or
erased*².
• If the mode pin input levels are changed (for example, from low to high) during a reset, the
state of ports with multiplexed address functions and bus control output pins (AS, RD, HWR)
will change according to the change in the microcomputer’s operating mode*³.
Therefore, care must be taken to make pin settings to prevent these pins from becoming output
signal pins during a reset, or to prevent collision with signals outside the microcomputer.
Notes: 1. Mode pin and FWE pin input must satisfy the mode programming setup time (t_MDS = 4
states) with respect to the reset release timing.
2. For precautions on applying and disconnecting FWE, see section 21B.15, Flash
Memory Programming and Erasing Precautions.
3. See appendix D, Pin States.
21B.8.2 User Program Mode
When set to user program mode, the chip can program and erase its flash memory by executing a
user program/erase control program. Therefore, on-board reprogramming of the on-chip flash
memory can be carried out by providing on-board means of FWE control and supply of
programming data, and storing a program/erase control program in part of the program area as
necessary.
To select user program mode, select a mode that enables the on-chip flash memory (mode 6 or 7),
and apply a high level to the FWE pin. In this mode, on-chip supporting modules other than flash
memory operate as they normally would in modes 6 and 7.
Page 822 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010