HD64F2636F20 Datasheet, PDF (585/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 14 Smart Card Interface
TDR
(1) Data write
(2) Transfer from
TDR to TSR
(3) Serial data output
Data 1
Data 1
Data 1
TSR
(shift register)
Data 1
; Data remains in TDR
Data 1
I/O signal line output
In case of normal transmission: TEND flag is set
In case of transmit error:
ERS flag is set
Steps (2) and (3) above are repeated until the TEND flag is set
Note: When the ERS flag is set, it should be cleared until transfer of the last bit (D7 in LSB-first
transmission, D0 in MSB-first transmission) of the next transfer data to be transmitted has
been completed.
Figure 14-5 Relation Between Transmit Operation and Internal Registers
I/O data
TXI
(TEND interrupt)
When GM = 0
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
12.5 etu
Guard
time
When GM = 1
11.0 etu
Legend:
Ds:
Start bit
D0 to D7: Data bits
Dp:
Parity bit
DE:
Error signal
Note: etu: Elementary time unit (time for transfer of 1 bit)
Figure 14-6 TEND Flag Generation Timing in Transmission Operation
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 535 of 1458