HD64F2636F20 Datasheet, PDF (482/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 12 Watchdog Timer
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
WDT0 Mode Select
TCSR0
WT/IT
Description
0
Interval timer mode: WDT0 requests an interval timer interrupt (WOVI)
from the CPU when the TCNT overflows
(Initial value)
1
Watchdog timer mode: A reset is issued when the TCNT overflows if the RSTE bit of
RSTCSR is set to 1^*
Note: * For details see section 12.2.3, Reset Control/Status Register (RSTCSR).
WDT1 Mode Select
TCSR1
WT/IT
0
1
Description
Interval timer mode: WDT1 requests an interval timer interrupt (WOVI)
from the CPU when the TCNT overflows
(Initial value)
Watchdog timer mode: WDT1 requests a reset or an NMI interrupt from
the CPU when the TCNT overflows
Bit 5—Timer Enable (TME): Selects whether TCNT runs or is halted.
Bit 5
TME
0
1
Description
TCNT is initialized to H'00 and halted
TCNT counts
(Initial value)
WDT0 TCSR Bit 4—Reserved Bit: A read operation on this bit always causes a 1 to be read out.
Every write operation on this bit is invalidated.
WDT1 TCSR Bit 4—Prescaler Select (PSS): This bit is used to select an input clock source for
the TCNT of WDT1.
See the descriptions of Clock Select 2 to 0 for details.
Page 432 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010