HD64F2636F20 Datasheet, PDF (610/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 15 I²C Bus Interface [Option]
(Only for the H8S/2638, H8S/2639, and H8S/2630)
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Bit 6—I²C Bus Interface Interrupt Enable (IEIC): Enables or disables interrupts from the I²C
bus interface to the CPU.
Bit 6
IEIC
0
1
Description
Interrupts disabled
Interrupts enabled
(Initial value)
Bit 5—Master/Slave Select (MST)
Bit 4—Transmit/Receive Select (TRS)
MST selects whether the I²C bus interface operates in master mode or slave mode.
TRS selects whether the I²C bus interface operates in transmit mode or receive mode.
In master mode with the I²C bus format, when arbitration is lost, MST and TRS are both reset by
hardware, causing a transition to slave receive mode. In slave receive mode with the addressing
format (FS = 0 or FSX = 0), hardware automatically selects transmit or receive mode according to
the R/W bit in the first frame after a start condition.
Modification of the TRS bit during transfer is deferred until transfer of the frame containing the
acknowledge bit is completed, and the changeover is made after completion of the transfer.
MST and TRS select the operating mode as follows.
Bit 5
MST
0
1
Bit 4
TRS
0
1
0
1
Operating Mode
Slave receive mode
Slave transmit mode
Master receive mode
Master transmit mode
(Initial value)
Page 560 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010