HD64F2636F20 Datasheet, PDF (247/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 8 Data Transfer Controller (DTC)
Bit n—DTC Activation Enable (DTCEn)
Bit n
DTCEn
0
1
Description
DTC activation by this interrupt is disabled
[Clearing conditions]
(Initial value)
• When the DISEL bit is 1 and the data transfer has ended
• When the specified number of transfers have ended
DTC activation by this interrupt is enabled
[Holding condition]
• When the DISEL bit is 0 and the specified number of transfers have not ended
(n = 7 to 0)
A DTCE bit can be set for each interrupt source that can activate the DTC. The correspondence
between interrupt sources and DTCE bits is shown in table 8-4, together with the vector number
generated for each interrupt controller.
For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR for reading and
writing. If all interrupts are masked, multiple activation sources can be set at one time by writing
data after executing a dummy read on the relevant register.
8.2.8 DTC Vector Register (DTVECR)
Bit
:
Initial value:
R/W
:
7
6
5
4
3
2
1
0
SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0
0
0
0
0
0
0
0
0
R/(W)*¹ R/W*² R/W*² R/W*² R/W*² R/W*² R/W*² R/W*²
Notes: 1. Only 1 can be written to the SWDTE bit.
2. Bits DTVEC6 to DTVEC0 can be written to when SWDTE = 0.
DTVECR is an 8-bit readable/writable register that enables or disables DTC activation by
software, and sets a vector number for the software activation interrupt.
DTVECR is initialized to H'00 by a reset and in hardware standby mode.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 197 of 1458