HD64F2636F20 Datasheet, PDF (990/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 23A Power-Down Modes [HD64F2636F, HD64F2638F, HD6432636F,
HD6432638F, HD64F2630F, HD6432630F, HD64F2635F, HD6432635F, HD6432634F]
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
On-Chip Supporting Module Interrupt: Relevant interrupt operations cannot be performed in
module stop mode. Consequently, if module stop mode is entered when an interrupt has been
requested, it will not be possible to clear the CPU interrupt source or the DTC activation source.
Interrupts should therefore be disabled before entering module stop mode.
Writing to MSTPCR: MSTPCR should only be written to by the CPU.
23A.6 Software Standby Mode
23A.6.1 Software Standby Mode
A transition is made to software standby mode when the SLEEP instruction is executed when the
SBYCR SSBY bit = 1 and the LPWRCR LSON bit = 0, and the TCSR (WDT1) PSS bit = 0. In
this mode, the CPU, on-chip supporting modules, and oscillator all stop. However, the contents of
the CPU’s internal registers, RAM data, and the states of on-chip supporting modules other than
the SCI, A/D converter, Motor control, PWM, HCAN and I/O ports, are retained. Whether the
address bus and bus control signals are placed in the high-impedance state.
In this mode the oscillator stops, and therefore power dissipation is significantly reduced.
23A.6.2 Clearing Software Standby Mode
Software standby mode is cleared by an external interrupt (NMI pin, or pins IRQ0 to IRQ5), or by
means of the RES pin or STBY pin.
• Clearing with an interrupt
When an NMI or IRQ0 to IRQ5 interrupt request signal is input, clock oscillation starts, and
after the elapse of the time set in bits STS2 to STS0 in SYSCR, stable clocks are supplied to
the entire chip, software standby mode is cleared, and interrupt exception handling is started.
When clearing software standby mode with an IRQ0 to IRQ5 interrupt, set the corresponding
enable bit to 1 and ensure that no interrupt with a higher priority than interrupts IRQ0 to IRQ5
is generated. Software standby mode cannot be cleared if the interrupt has been masked on the
CPU side or has been designated as a DTC activation source.
• Clearing with the RES pin
When the RES pin is driven low, clock oscillation is started. At the same time as clock
oscillation starts, clocks are supplied to the entire chip. Note that the RES pin must be held low
until clock oscillation stabilizes. When the RES pin goes high, the CPU begins reset exception
handling.
Page 940 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010