HD64F2636F20 Datasheet, PDF (963/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 22A Clock Pulse Generator
(H8S/2636 Group, H8S/2638 Group, H8S/2630 Group)
Handling Pins when Subclock not Required: If no subclock is required, connect the OSC1 pin
to VSS and leave OSC2 open, as shown in figure 22A-10.
OSC1
OSC2
Open
Figure 22A-10 Pin Handling when Subclock not Required
22A.8 Subclock Waveform Generation Circuit
To eliminate noise from the subclock input to OSCI, the subclock is sampled using the dividing
clock φ. The sampling frequency is set using the NESEL bit of LPWRCR. For details, see section
23A.2.3, 23B.2.3, Low Power Control Register (LPWRCR).
No sampling is performed in subactive mode*, subsleep mode*, or watch mode*.
Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the
U-mask and W-mask versions only.
These functions cannot be used with the other versions.
22A.9 Note on Crystal Resonator
Since various characteristics related to the crystal resonator are closely linked to the user’s board
design, thorough evaluation is necessary on the user’s part, for both the mask versions and
F-ZTAT versions, using the resonator connection examples shown in this section as a guide. As
the resonator circuit ratings will depend on the floating capacitance of the resonator and the
mounting circuit, the ratings should be determined in consultation with the resonator
manufacturer. The design must ensure that a voltage exceeding the maximum rating is not applied
to the oscillator pin.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
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