HD64F2636F20 Datasheet, PDF (773/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 19 Motor Control PWM Timer
19.2.5 PWM Cycle Registers 1 and 2 (PWCYR1, PWCYR2)
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
——————
Initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Read/Write — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
PWCYR is a 16-bit read/write register that sets the PWM conversion cycle. When a PWCYR
compare match occurs, PWCNT is cleared and data is transferred from the buffer register
(PWBFR) to the duty register (PWDTR). PWCYR1 is used for the channel 1 conversion cycle
setting, and PWCYR2 for the channel 2 conversion cycle setting.
PWCYR should be written to only while PWCNT is stopped. A value of H'FC00 must not be set.
PWCYR is initialized to H'FFFF upon reset, and in standby mode, watch mode*, subactive
mode*, subsleep mode*, and module stop mode.
Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the
U-mask and W-mask versions, and H8S/2635 Group only.
These functions cannot be used with the other versions.
Compare match
PWCNT
(lower 10 bits)
0
1
PWCYR
(lower 10 bits)
Compare match
N−2 N−1 0
1
N
Figure 19-3 Cycle Register Compare Match
REJ09B0103-0800 Rev. 8.00
May 28, 2010
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