HD64F2636F20 Datasheet, PDF (965/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 22B Clock Pulse Generator
(H8S/2639 Group, H8S/2635 Group)
Section 22B Clock Pulse Generator
(H8S/2639 Group, H8S/2635 Group)
22B.1 Overview
The chip has a built-in clock pulse generator (CPG) that generates the system clock (φ), the bus
master clock, and internal clocks.
The clock pulse generator consists of an oscillator, PLL (phase-locked loop) circuit, system clock
selection circuit, medium-speed clock divider, bus master clock selection circuit, and subclock
divider. The frequency can be changed by means of the PLL circuit in the CPG. Frequency
changes are performed by software by means of settings in the system clock control register
(SCKCR) and low-power control register (LPWRCR).
22B.1.1 Block Diagram
Figure 22B-1 shows a block diagram of the clock pulse generator.
EXTAL
XTAL
Clock
oscillator
LPWRCR
STC1, STC0
PLL circuit
(×1, ×2, ×4)
φSUB
System
clock
selection
circuit
SCKCR
SCK2 to SCK0
Medium-
speed
clock divider
φ/2 to
φ/32
φ
Bus
master
clock
selection
circuit
Subclock
divider (1/128)
System clock Internal clock to
to φ pin supporting modules
Bus master clock
to CPU and DTC
WDT1 count clock
Legend:
LPWRCR: Low-power control register
SCKCR: System clock control register
Figure 22B-1 Block Diagram of Clock Pulse Generator
REJ09B0103-0800 Rev. 8.00
May 28, 2010
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