HD64F2636F20 Datasheet, PDF (40/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

16.2.4 Mailbox Configuration Register (MBCR) ........................................................... 624
16.2.5 Transmit Wait Register (TXPR) .......................................................................... 625
16.2.6 Transmit Wait Cancel Register (TXCR).............................................................. 626
16.2.7 Transmit Acknowledge Register (TXACK) ........................................................ 627
16.2.8 Abort Acknowledge Register (ABACK) ............................................................. 628
16.2.9 Receive Complete Register (RXPR).................................................................... 629
16.2.10 Remote Request Register (RFPR) ....................................................................... 630
16.2.11 Interrupt Register (IRR)....................................................................................... 631
16.2.12 Mailbox Interrupt Mask Register (MBIMR) ....................................................... 636
16.2.13 Interrupt Mask Register (IMR) ............................................................................ 637
16.2.14 Receive Error Counter (REC) .............................................................................. 640
16.2.15 Transmit Error Counter (TEC)............................................................................. 640
16.2.16 Unread Message Status Register (UMSR)........................................................... 641
16.2.17 Local Acceptance Filter Masks (LAFML, LAFMH)........................................... 642
16.2.18 Message Control (MC0 to MC15) ....................................................................... 644
16.2.19 Message Data (MD0 to MD15) ........................................................................... 648
16.2.20 Module Stop Control Register C (MSTPCRC).................................................... 650
16.3 Operation .......................................................................................................................... 651
16.3.1 Hardware and Software Resets ............................................................................ 651
16.3.2 Initialization after Hardware Reset ...................................................................... 654
16.3.3 Transmit Mode..................................................................................................... 659
16.3.4 Receive Mode ...................................................................................................... 665
16.3.5 HCAN Sleep Mode.............................................................................................. 671
16.3.6 HCAN Halt Mode................................................................................................ 673
16.3.7 Interrupt Interface ................................................................................................ 673
16.3.8 DTC Interface ...................................................................................................... 675
16.4 CAN Bus Interface............................................................................................................ 676
16.5 Usage Notes ...................................................................................................................... 677
Section 17 A/D Converter................................................................................................. 681
17.1 Overview........................................................................................................................... 681
17.1.1 Features................................................................................................................ 681
17.1.2 Block Diagram..................................................................................................... 682
17.1.3 Pin Configuration................................................................................................. 683
17.1.4 Register Configuration......................................................................................... 684
17.2 Register Descriptions ........................................................................................................ 685
17.2.1 A/D Data Registers A to D (ADDRA to ADDRD) ............................................. 685
17.2.2 A/D Control/Status Register (ADCSR) ............................................................... 686
17.2.3 A/D Control Register (ADCR) ............................................................................ 689
17.2.4 Module Stop Control Register A (MSTPCRA) ................................................... 690
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REJ09B0103-0800 Rev. 8.00
May 28, 2010