HD64F2636F20 Datasheet, PDF (1006/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 23B Power-Down Modes [HD64F2636UF, HD6432636UF, HD64F2638UF, HD6432638UF,
HD64F2638WF, HD6432638WF, HD64F2639UF, HD6432639UF, HD64F2639WF, HD6432639WF,
HD64F2630UF, HD6432630UF, HD64F2630WF, HD6432630WF, HD6432635F, HD64F2635F, HD6432634F]
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Bits 6 to 4—Reserved: These bits are always read as 0 and cannot be modified.
Bit 3—Frequency Multiplication Factor Switching Mode Select (STCS): Selects the operation
when the PLL circuit frequency multiplication factor is changed.
Bit 3
STCS
0
1
Description
Specified multiplication factor is valid after transition to software standby mode, watch
mode, or subactive mode
(Initial value)
Specified multiplication factor is valid immediately after STC bits are rewritten
Bits 2 to 0—System Clock Select (SCK2 to SCK0): These bits select the bus master clock in
high-speed mode, medium-speed mode, and subactive mode.
Set SCK2 to SCK0 all to 0 when shifting to operation in watch mode or subactive mode.
Bit 2
SCK2
0
1
Bit 1
SCK1
0
1
0
1
Bit 0
SCK0
0
1
0
1
0
1
—
Description
Bus master in high-speed mode
Medium-speed clock is φ/2
Medium-speed clock is φ/4
Medium-speed clock is φ/8
Medium-speed clock is φ/16
Medium-speed clock is φ/32
—
(Initial value)
Page 956 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010